Digital systems communicate data both internally (e.g., between a processor and memory) and externally (e.g., between devices, such as a host computer and a mobile wireless communication device) on “buses.” Parallel buses are characterized by a separate data line for each bit in a data unit, such as a byte or word. In contrast, a serial bus comprises a single logical data line, with bit values being transmitted successively. A bus line—whether a serial bus or a single bit of parallel bus—may be implemented as a single-ended line, wherein a voltage or current varies with respect to a reference, or ground, value. Alternatively, to improve reliability at high data rates and/or in an electrically noisy environment, a bus line may be implemented as a differential pair, wherein the voltage or current on separate conductors are controlled in opposite directions, and a datum value is represented as the relative value between the two. Buses may be bidirectional, with two (or more) controllers operative to drive data values onto the bus.
The Universal Serial Bus (USB) is a bidirectional serial bus specification designed to establish communication between devices and a host controller. Originally designed for personal computers, the USB is intended to replace many varieties of serial and parallel ports. For example, USB connects many computer peripherals such as mice, keyboards, digital cameras, printers, personal media players, flash drives, external hard drives, and the like. Although designed for personal computers, USB has found application in a broad variety of other data communication contexts. USB signals are transmitted on a braided pair data cable with 90Ω±15% Characteristic impedance, labeled D+ and D−. Prior to USB 3.0, these collectively use half-duplex differential signaling to reduce the effects of electromagnetic noise on longer lines. Transmitted signal levels are 0.0-0.3 volts for low and 2.8-3.6 volts for high in full speed mode (12 Mbits/s) and low speed mode (1.5 Mbits/s), and −10-10 mV for low and 360-440 mV for high in hi-speed mode (480 Mbits/s). In full speed mode the cable wires are not terminated, but the hi-speed mode has termination of 45Ω to ground, or 90Ω differential to match the data cable impedance, reducing interference of particular kinds.
USB devices are tested for compliance with the USB technical specifications. One tool used in the testing is an eye diagram. The diagram measures a data signal's rise time, fall time, undershoot, overshoot, and jitter. With a USB 2.0 eye diagram, the test system performs the measurements over one USB data packet (488 bits). After receiving test data from an oscilloscope, testing scripts take the data from each bit period (2.0833 ns) and overlay all bits onto a USB 2.0 eye mask.
Because the USB is bidirectional, many systems implementing active switching of drivers on the D+ and D− lines, for example by means of CMOS switches, to prevent collisions when another entity drives data on the bus. This inevitably adds series resistance to the source impedance used to drive the lines, which often have a high capacitance. For example, a realistically sized CMOS switch may add 5-10Ω—a significant increase considering the specified termination to ground is 45Ω. This may reduce signal transition slew rates (i.e., rise and fall times), resulting in noncompliance of the eye diagram test at the near and/or far end of the link.
Accordingly, a need exists in the art for a strategy that will overcome the slow and/or reduced amplitude transitions caused parasitic RC integration time constants. Additionally, some equalization for the limited frequency response of the USB cable would be beneficial. Because the DC conductivity of the wire connections between both ends of the link must be preserved, conventional high-pass filter sections cannot simply be inserted into the bus line. Directional, active filters will also cause a significant problem since either end of the link can become the master and begin sourcing current into the serial connection wires. Most conventional equalizer topologies will cause a disturbance to the desired characteristic impedance of the serial line (i.e., 45Ω to ground or 90Ω differential). Thus, a solution to the deleterious effects of parasitic RC integration time constants, that does not significantly alter termination impedances, is desired.